This paper explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Combined with a performance simulator, McPAT enables architects to consistently quantify the cost of new ideas and assess tradeoffs of different architectures using new metrics like energy-delay-area2 product (EDA2P) and energy-delay- area product (EDAP). McPAT has a flexible XML interface to facilitate its use with many performance simulators.
At the circuit and technology levels, McPAT supports critical-path timing mod- eling, area modeling, and dynamic, short-circuit, and leak- age power modeling for each of the device types forecast in the ITRS roadmap including bulk CMOS, SOI, and double- gate transistors. At the microarchitectural level, McPAT includes models for the fundamental components of a chip multipro- cessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, integrated memory con- trollers, and multiple-domain clocking. This paper introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehen- sive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond.
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